1. Field of the Invention
This invention relates to methods for fabricating a semiconductor package, and, more particularly, to a method for fabricating a semiconductor package having a redistribution structure.
2. Description of Related Art
With the rapid development of the electronic industry, electronic products have a variety of impressive functionalities. In order to meet the compact-size and low-profile requirements, a fan-out type semiconductor package is brought to the market.
FIGS. 1A-1D are cross-sectional views illustrating a method for fabricating a fan-out type semiconductor package 1 according to the prior art.
As shown in FIG. 1A, a carrier member 10 is provided, and an adhesive layer 11 is formed on the carrier member 10.
A plurality of semiconductor elements 12 are disposed on the adhesive layer 11. Each of the semiconductor elements 12 has opposing active surface 12a and non-active surface 12b, a plurality of electrode pads 120 are disposed on the active surface 12a, and the active surface 12a is adhered to the adhesive layer 11.
As shown in FIG. 1B, an insulating layer 13 is formed by a lamination process on the adhesive layer 11 to cover the semiconductor elements 12.
As shown in FIG. 1C, the insulating layer 13 is thermally cured, and the carrier member 10 and the adhesive layer 11 are removed, to expose the active surface 12a of the semiconductor element 12.
As shown in FIG. 1D, a redistribution layer (RDL) process is performed, and a redistribution structure 14 is formed on the insulating layer 13 and the active surface 12a of the semiconductor element 12. The redistribution structure 14 is electrically connected to the electrode pads 120 of the semiconductor element 12.
An insulating protection layer 15 is formed on the redistribution structure 14, and exposes a portion of a surface of the redistribution structure 14, for a conductive element 16 such as a solder bump to be engaged therewith.
However, during the lamination process of the method for fabricating the semiconductor package 1 according to the prior art the insulating layer 13 (i.e., the thermally curing process) generates a great stress and the great stress is dispersed by the carrier member 10. As the carrier member 10 is removed, the great stress causes warpage of the insulating layer 13, as shown in FIG. 1D′. Therefore, the redistribution structure 14 misaligns with the electrode pads of the semiconductor element 12. As the carrier member 10 becomes larger and larger, the location tolerance of the semiconductor element 12 increases accordingly. As a result, the redistribution structure 14 cannot be connected to the electrode pads 120 due to too great the warpage, and the electrical connection between the redistribution structure 14 and the semiconductor element 12 is greatly affected, which results in low yield and poor reliability.
Therefore, how to solve the problems of the prior art is becoming an urgent issue in the art.